module test (SW, HEX2, HEX1, HEX0)

input [8:0]SW;

output [6:0] HEX2, HEX1, HEX0;

wire [3:0] tram, chuc, dvi;

assign tram=SW/100;

assign chuc=(SW%100)/10;

assign dvi=SW%10;

decoder disTram (tram, HEX2);

decoder disChuc (chuc, HEX1);

decoder disDvi (dvi, HEX0);

endmodule

module decoder (in, out)

input [3:0]in;

output reg [0:6]out;

always @(in)

case(in)

0: out<=7'b0000_001;

1: out<=7'b1001_111;

2: out<=7'b0010_100;

3: out<=7'b0000_110;

4: out<=7'b1001_100;

5: out<=7'b0100_100;

6: out<=7'b0100_000;

7: out<=7'b0001_111;

8: out<=7'b0000_000;

9: out<=7'b0000_100;

default: out<=7'b1111_111;

endcase

endmodule