module test (CLOCK_50, LEDG);
input CLOCK_50;
output reg [7:0] LEDG;
reg [25:0]t;
reg style;
wire clk=t[25];


always @(posedge CLOCK_50)
t=t+1;

always @(posedge clk)
begin
if(LEDG==8'h00)
LEDG=8'b1000_0000;
else
case(style)
0: begin style<=LEDG[1]?1:0; LEDG<=LEDG>>1; end
1: begin style<=LEDG[6]?0:1; LEDG<=LEDG<<1; end
endcase
end
endmodule