module test (SW, HEX1, HEX0);

input [7:0]SW;

output [0:6] HEX0, HEX1;

wire [3:0]a, b;

wire [4:0]sum;

wire [3:0]chuc, donvi;

assign a=SW[7:4];

assign b=SW[3:0];

assign sum=a+b;

assign chuc=sum/10;

assign donvi=sum%10;

decoderBCD disCHUC (chuc, HEX1);

decoderBCD disDONVI (donvi, HEX0);

endmodule

module decoderBCD (in, out);

input [3:0]in;

output [0:6]out;

reg [0:6]out;

always @(in)

case (in)

0: out<=7'b0000_001;

1: out<=7'b1001_111;

2: out<=7'b0010_010;

3: out<=7'b0000_110;

4: out<=7'b1001_100;

5: out<=7'b0100_100;

6: out<=7'b0100_000;

7: out<=7'b0001_111;

8: out<=7'b0000_000;

9: out<=7'b0000_100;

default: out<=7'b1111_111;

endcase

endmodule