Lưu Hoàng Hiệp 0820053

Trần Duy Lâm 0820085

Trương Minh Phương 0820124

Nguyễn Phúc Thành 0820151

Ngày nộp: 4/5/2011

Số tờ: 3

1)

Rising propagation delay= R/2*8C+(R/2+R/2)*6C=10RC

Falling propagation delay=R/2*C+(R/2+R/2)*6C= 6.5RC

2)The 4x inverter have 12 units of input capacitance. The logical effort and parasitic delay don’t change although the size of transistor changes

3)

a)F=GxH=4/3x6=8

   N=2

  P=2+1=3

We have fomula

b)F=GxH=5/3x6=10

N=2

P=1+2=3

4)F=20000/7.2=2777.7

Look up table 4.1, we have the fastest inverter string is the string with 6 stages and

 stage effort will lie in the range 3.2 – 4 delay units

5)

a)

b)

c)

d)

H=1: the fastest is b with D=8.3

H=5: the fastest is b with D=12.5

H=20:the fastest is d with D=17.3

6)

F=BGH=4x16x16x4x9/3x6/3x5/3=40960

P=4+4+4+2+1=15

=>x=10x1/8.4=1.2

    y=16x1.2x5/3/8.4=3.8

    z=16x3.8x6/3/8.4=14.5

   t=14.5x9/3/8.4=5.2

7) The logical effort of 1a: 4/3*4/3=16/9

    The logical effort of 1b: =4